1. Field
The present disclosure relates generally to pulse width recovery, and more particularly, to pulse width recovery in clock dividers.
2. Background
In a system on a chip (SoC)/integrated circuit (IC), a clock divider is often used to generate lower frequency clock signals from an existing higher frequency clock signal. With some divider values (e.g., integer divider values), a balanced duty cycle (e.g., 50%) may be maintained. However, for some divider values (e.g., fractional divider values), the duty cycle may be reduced, which reduces a pulse width of the divided clock signal. The reduced pulse width may require design changes to speed up the IC/SoC and/or to reduce a clock frequency provided to the IC/SoC. Methods and apparatuses are therefore needed for restoring a balanced duty cycle to a divided clock signal.